2/15/2013 Megan Kelly
Written by Megan Kelly
Electrical and Computer Engineering Assistant Professor Shobha Vasudevan has received a National Science Foundation CAREER Award totaling $450,000 and spanning 5 years. CAREER Awards provide resources to promising new professors who submit innovative proposals.
The award will be used to advance GoldMine, a software system Vasudevan and her team developed to make the system-on-a-chip (SoC) assertion-based verification process smoother and more efficient.
An “SoC” integrates computer components into a single integrated circuit, or chip. It can contain digital, analog, mixed-signal and radio-frequency functions, and typically is used with powerful processors. The chips are verified for logical correctness before being sent to foundry. Often, the verification process uses assertions, or embedded design checks used to catch bugs early.
“Assertion based checking requires crafting high coverage, irredundant assertions that can take many man-months to arrive at,” Vasudevan said. “Given that design verification is considered a serious bottleneck in the semiconductor design cycle, the resources and time spent in writing assertions manually is significant.”
GoldMine automates the assertion generation process, thereby dramatically decreasing the manual intervention in this process. The system combines data mining with formal verification to automatically generate complex assertions.
“GoldMine comprises a synergistic interaction between two technologies- data mining is computationally efficient at coming up with inferences about the system, but lacks context,” said Vasudevan, who previously applied a similar principle to computer-aided design (CAD). “Formal verification has computational capacity limitations, but is excellent at providing context."
In addition to assertion generation, GoldMine has been applied to test generation in the design verification phase. The technology has managed to achieve test coverage closure, providing a metric for test completeness to designers. In doing this, it solves a problem that has been an open challenge to the design verification/validation community for decades.
Her team first experimented with GoldMine using the Rigel Project, a U of I parallel computing initiative, where they obtained valuable constructive criticism to improve the system. The project has since attracted industry interest. Vasudevan is working with a number of semiconductor companies to explore the possibility of incorporating GoldMine into their verification processes.
Vasudevan hopes GoldMine will lead to other innovations in the assertion-based verification process.
“It will be a quantum leap in the state-of-the-art in hardware verification,” she said. “The grand dream for Computer Aided Design is to automate every human process in chip generation. GoldMine takes you closer to the dream.”