High-level synthesis on fire: research receives recognition from academia, industry
CSL and Electrical and Computer Engineering Professor Deming Chen is an active leader involved in groundbreaking research in the area of high-level synthesis (HLS). His work recently garnered him and his students three HLS grants and one best paper award in this exciting field.
High-level synthesis is a new trend in the design automation field for generating register transfer level (RTL) code, such as Verilog or VHDL code, automatically from design entries written in high-level languages, such as C or C++. In general, it has been shown that the code density and simulation time can be improved by 10X and 100X, respectively, when moved to high-level synthesis from RTL synthesis. Such an improvement in efficiency is much needed for design in the deep submicron era.
During previous research, Chen and his team used the polyhedral model to describe the mathematical principles that drive different types of code transformations. These models are typically used for CPU compilers, but Chen and his team realized they could also be adopted for work on high-level synthesis as well.
“The key issue is to identify the difference between code generation for CPU and for circuits, such as custom hardware or FPGA,” Chen said. “After these differences became clear to us, we could then systematically re-examine the design choices for polyhedral code generation on HLS by looking at different techniques, such as polyhedral separation evaluation, loop bound tuning and bounding box in loop tiling.”
Chen collaborated with his student Wei Zuo and other researchers, including Dr. Peng Li of Peking University and professors Louis-Noel Pouchet and Jason Cong of University of California at Los Angeles, on the project. Zuo was a visiting Ph.D. student from Beijing Institute of Technology who stayed for two years in Chen’s lab working on HLS with polyhedral models. She plans to return as an electrical and computer engineering graduate student in January 2014.
“We found out that in order to improve the opportunity for parallelization, the polyhedral model could be very useful to guide loop transformations, such as loop tiling,” Zuo said.
With these new techniques, the team achieved a 17.5 percent reduction in average latency, a 55.1 percent reduction in average resource utilization and a 59.8 percent reduction in average energy consumption. This work was supported in part by the Center for Future Architectures Research (C-FAR), which is part of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA.
Additionally, according to Chen, the semiconductor industry has been trying to achieve high design productivity and high design quality, but the processes have been highly complex, time consuming and costly. Companies are looking for efficient design strategy to improve overall productivity and deliver products that are very energy efficient and quick to the market. High-level synthesis is promising to achieve these goals.
Chen recently received a three-year $300,000 grant from Intel to continue research on customized polyhedral compilation for low-power high-level system-on-a-chip (SoC) synthesis. Pouchet of UCLA joins the effort as a subcontract researcher for this project.
“Intel is very interested in HLS for SoC and their goal is to design smart-energy SoCs faster,” Chen said. “We will be using the polyhedral model as the backbone for a new framework to automatically define hardware/software boundary and use HLS techniques to facilitate such a process.”
Chen is hoping to develop optimization techniques that can explore the overall design space more efficiently and identify near optimal design solutions, so in the end they will develop highly efficient and high performance SoC circuits in much faster design time.
On top of this work, Chen and his collaborator, David Pan at the University of Texas at Austin, recently received a three-year, $350,000 grant from NSF and the Semiconductor Research Corporation (SRC). The project will take a cross-layer approach that combines HLS and physical design layout together to improve SoC reliability metrics given power and performance budget. Furthermore, in early November, Chen and his collaborator, Subhasish Mitra of Stanford University, received a separate three-year, $390,000 grant from SRC that will support another HLS project. The project will use HLS techniques to dramatically improve the post-silicon validation task for complex SoC designs, which hasn’t been explored in the research community before.
“Overall, high-level synthesis is on fire,” Chen said.