Illinois researchers pursue the best of both worlds – top performance and high programmability – under new DARPA project
You might not think of high-performance computing and high programmability as things that go hand in hand—unless you’re CSL researchers Wen-mei Hwu and Deming Chen, or another member of their recently funded Dynamic Data-Aware Reconfiguration, Integration and Generation (DDARING) team.
Led by the Georgia Institute of Technology, DDARING also has team members from the University of Michigan, the University of Southern California, and the University of Illinois at Urbana-Champaign. The different universities are contributing a total of eight researchers with distinct areas of expertise, who will work on different parts of the effort to improve how computers handle information.
“We needed a team working cooperatively to address this big challenge,” said Chen, an electrical and computer engineering (ECE) professor. “That’s why we formed a team among the best researchers across different universities working together to achieve the goal. We want to make sure the whole is bigger than the sum of the parts.”
Currently, many computing platforms have the flexibility to work with many applications and a variety of operating systems, but they aren’t as high-performing as computing platforms that use ASIC chips. An ASIC (“application-specific integrated circuit”) chip is designed to perform a specific task with very high performance and efficiency, but it can perform only that single task; it has no programmability or flexibility. The DDARING team is set to pursue the challenging goal of approaching the high processing capability of an ASIC chip, without losing the programming flexibility of standard computing platforms.
“To overcome this critical challenge, our approach is to build reconfigurable software through smart compiler techniques targeting dynamically reconfigurable hardware to achieve near-ASIC performance and efficiency,” said Chen.
Chen and Hwu’s piece of the DDARING project is developing a program in which dynamic changes of different algorithmic phases and data patterns take place. Hwu is creating highly optimized code for the application. He is making sure that the program—a compiler—selects the right code versions for the application and executes the functions properly on the dynamically reconfigured hardware. Chen is using machine learning to train the compiler on what to do while the algorithm phases and data are changing. That will involve offline training that uses machine learning techniques, and online inferencing that makes code optimization and hardware configuration decisions. The resulting decisions will then be passed to the hardware, and a check will ensure that the hardware is configured as it should be.
“The main two parts of our tasks are figuring out how to reconfigure the hardware, and then compiling and generating the code to take advantage of the reconfigured hardware,” said Hwu, who is the acting head of the ECE department.
Hwu likens the process to trying to reconfigure a highway to reduce congestion. Normally, of course, highways have the same number of lanes on each side, under the assumption that equal amounts of traffic will go in the two directions. But if a large traffic imbalance between the two sides were to occur, in theory you could reduce congestion by allowing traffic on the overloaded side to use more than half of the road’s lanes.
"Although it is extremely difficult to achieve that kind of reconfiguration architecture for a highway, it is actually totally possible when we are in the computer architecture field,” Hwu said.
The project is funded by the Defense Advanced Research Projects Agency (DARPA) and is expected to take two and a half years, with a possibility for further extension. It is part of the Software Defined Hardware (SDH) program under the new DARPA Electronics Resurgence Initiative (ERI).