Breaking the 1000-core barrier: New parallel architecture provides foundation for breakthroughs in imaging, more

2/14/2013 Kim Gudeman

University of Illinois researchers are developing a 1000-core architecture that will offer increased computational power for parallel computing applications.

Written by Kim Gudeman

University of Illinois researchers are developing a 1000-core architecture that will offer increased computational power for parallel computing applications.

The Rigel Architecture will usher in a new generation of multi-core chips, leading to advancements in video gaming, video conferencing, medical imaging and much more.
The Rigel Architecture will usher in a new generation of multi-core chips, leading to advancements in video gaming, video conferencing, medical imaging and much more.
The Rigel Architecture will usher in a new generation of multi-core chips, leading to advancements in video gaming, video conferencing, medical imaging and much more.

Through its innovative design, the Rigel Architecture will enable faster, more powerful processing of video, images, speech, graphical data, and physical simulation, and pave the way for emerging applications that utilize advanced processing such as computer vision and machine learning. A Rigel chip could potentially provide many teraflops of performance -- substantially higher compute power than is currently available on multicore chips.

“In designing the Rigel Architecture, we made careful choices between performance, power, and programmability, rethinking from scratch what should be done in silicon,” says Sanjay Patel, the project’s lead researcher and professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. “The economy of the architecture enables us to achieve levels of integration, such as 1000+ cores on a single chip in today’s semiconductor fabrication technology, beyond what is possible with other multicore architectures.”

The technology, outlined in “Rigel: An Architecture and Scalable Programming Interface for a 1000-core Accelerator,” was presented at the International Symposium on Computer Architecture in June and at the Symposium on Application Accelerators in High Performance Computing in July.

Rigel is one component of a major parallel computing initiative at Illinois called Project Orion. Orion seeks to define the parallel computing platform of the future through simultaneous advancement in parallel architectures, parallel programming tools, visual computing applications, and parallel programming education.

“Rigel leverages our experience with parallel applications and programming tools to provide a significant leap forward in single-chip computing power, thus enabling new types of applications that would not be possible otherwise,” says Wen-mei Hwu, director of Project Orion and professor of Electrical and Computer Engineering at University of Illinois at Urbana-Champaign.

Parallel computing provides the necessary horsepower for emerging visual computing applications, such as real-time medical imaging, next-generation video, 3D and 4D immersive telepresence, and ultra-realistic video gaming. Current architectures such as graphics processing units (GPUs) are increasingly used on such applications for their computational capabilities, but require extra programming effort due to their architectural constraints.

Because of the unique design of its processing cores, interconnects, and memories, Rigel is easier to program and more cost-effective than other multicore solutions. In addition, it will offer higher performance per watt. It is well suited for applications that are visual in nature.

Scaling to thousands of cores on a single chip is technically challenging. But the Illinois researchers have found clever ways to organize computational resources on Rigel so that programmers can map diverse algorithms and tap into the computational capability of the chip.

Compared to existing accelerators, which contain domain-specific hardware, specialized memories, and/or restrictive programming models, Rigel is more flexible and provides a straightforward target for a broader set of applications.

“Breaking through the 1000-core barrier is a significant milestone and we are demonstrating that it is possible to do this today in a way that leverages productive parallel programming methodologies,” says Patel.

About the Coordinated Science Laboratory
The Coordinated Science Laboratory at the University of Illinois is one of the nation's premier multidisciplinary research laboratories, focusing on information technology at the crossroads of computing, control and communications. Created in 1951 to address urgent military needs associated with the Korean War, CSL continues to transform society by developing and deploying new technologies in areas such as defense, medicine, environmental sciences, robotics, life-enhancement for the disabled and aeronautics.

About Parallel@Illinois
Parallel@Illinois represents the breadth of Illinois activities and resources invested in pioneering and promoting parallel computing research and education. Current efforts include the Blue Waters petascale supercomputer, a global Cloud Computing Testbed, a CUDA Center of Excellence, the Institute for Advance Computing Applications & Technologies, the OpenSPARC Center of Excellence, and the Universal Parallel Computing Research Center.


Share this story

This story was published February 14, 2013.