CAEML aims to improve pre-manufacturing testing
The “try before you buy” approach has long been a way to ensure that customers will be happy with a purchase. For the manufacturers and designers of electronic devices, “try before you manufacture” has also been a strategy; but with the intricacy of today’s designs, it has become extremely complicated. Based on suggestions from its industry partners, the Center for Advanced Electronics through Machine Learning (CAEML) is working to create models that could improve the efficacy of the process.
“We’re interested in using state-of-the-art machine learning tools to predict how a given electronic device is going to behave in new circumstances,” said CSL’s Max Raginsky, associate professor of electrical and computer engineering and William L. Everitt Fellow. “The goal is to ensure that, despite variations in operating conditions or parameters, we can still make accurate predictions about what it is going to do.”
When electronic devices are mass-manufactured, there are unavoidable minor random variations in their parameters. The technical term for this is “process variations.” These small differences could potentially cause problems if the semiconductor characteristics are just a bit off, or if the part has a slightly different shape. The success of a product, and ultimately a company, depend on the ability to understand how these minute changes affect the performance of the device.
The main challenge faced by manufacturers is that any sufficiently complex electronic device has a huge number of parameters. For example, the main processor in an iPhone has more than two billion transistors, and each comes with a handful of device parameters. In addition, the process variations that impact these parameters are inherently random. As a consequence, the operating characteristics of the device depend on these parameters in a highly nonlinear and random fashion. To overcome these obstacles, CAEML researchers seek to model the entire probability distribution of the device’s behavior.
“We’ll look at a product batch, and each device will be slightly different. While we have no precise idea about the differences, we can subject them to the same stimulus and model the probability distribution of the resulting response,” Raginsky said. “Based on the data we collect from observations, we can determine a model that we can later use to make an inference about how this device will behave. This is an exciting research area that integrates state-of-the-art machine learning tools, such as deep neural nets, with ideas from nonlinear control and dynamical systems.”
An example of this behavior prediction involves cell phones and static discharge. When a phone rubs against fabric in someone’s pocket, it causes static discharge. If a batch of phones had a defect that made them unable to work in the presence of the discharge, this could cause major problems, rendering the phones useless due to a daily activity. The models being built by CAEML would be able to predict that this slight change in a phone’s makeup would cause it to be negatively affected by electrostatic discharge static, and it shouldn’t be manufactured without first effecting design changes to improve the robustness.
This research was brought to the attention of CAEML by their Industry University Cooperative Research Center (IUCRC). Each year the industry partners of the center vote on what research they see as most beneficial to their businesses. This allows CAEML to stay relevant in what industry needs and to solve technical challenges the industry has.
“Uniquely, CAEML has brought together electronics designers, EDA tool developers, and theorists working in the fields of control, information and machine learning theory,” said Elyse Rosenbaum, CAEML director and the Melvin D. and Anne Louise Hassebrock Professor of Electrical and Computer Engineering. “The problems we work on are those that the center’s industry members find most vexing. The diverse mix of participants have settled on a research portfolio with a few overarching goals, e.g. eliminating time-consuming drudgery from the IC design process, identification of design points at which performance and robustness against variability are balanced, security and reliability.”