Vasudevan to collaborate with Synopsys on verification
CSL Assistant Professor Shobha Vasudevan has begun a collaboration with Synopsys in the area of functional verification. Functional verification is the process of determining that a particular hardware design conforms to its specifications and performs as intended. In concert with this collaboration, Synopsys has entered into a licensing agreement for one of the tools developed by Vasudevan's group, evaluating its potential for commercialization.
“It is very exciting to have one's work recognized by the leading company in electronic design automation and be part of their next generation vision for EDA products,” said Vasudevan, an assistant professor of electrical and computer engineering. "I hope that the industrial user feedback will enhance my tool, and they will be able to take the technology developed at Illinois to the end users successfully.”
Synopsys is a global leader providing software, IP, and services used to accelerate innovation in chips and electronic systems. The company has offices located throughout North America, Europe, Japan, Asia and India.
Synopsys approached Vasudevan regarding working together, due to some state-of-the-art verification computer-aided design (CAD) tools invented by her group. She visited the company last year for multiple discussions with the technical as well as top management teams.Vasudevan will be working closely with several members of the verification team in Synopsys during this collaboration.
In addition to this collaboration with Vasudevan, Synopsys provided a research award for use in the Coordinated Science Lab for research on applying statistical techniques to hardware design verification. The research team for the current Synopsys collaboration consists of ECE graduate student Samuel Hertz and three ECE undergraduates.
Vasudevan has spearheaded a research team that has developed several CAD tools in the electronic design automation (EDA) field, including STAR/HYBRO (generating high coverage simulation vectors for register transfer level of the hardware design cycle), GoldMine (automatic assertion generation), SHARPE (providing formal statistical timing/power analysis at the higher levels of design), and PRECIS (automatic assertion generation in software). Her group has also developed techniques and tools for computing assertion coverage in RTL and in field programmable gate array-based emulation.
GoldMine, Vasudevan's most popular research software, has been developed by many ECE graduates and undergraduates over the past four years. It is available for research use at goldmine.csl.illinois.edu. Other software tools from Vasudevan’s lab can be obtained from her website or by contacting the corresponding authors.
Vasudevan received an NSF CAREER Award in 2010 for her work on an automated assertion generation. In 2011 she received the YWCA Leadership Award in Science from the YWCA chapter of Champaign-Urbana for her research accomplishments and her efforts to mentor young women in engineering.
Vasudevan is excited at the prospect of this collaboration and what it can mean for ECE and the University. “At this point, verification research at ECE Illinois is eliciting a lot of interest from the EDA industry,” she said.