Shaloo Rakheja

Shaloo Rakheja
Shaloo Rakheja
Associate Professor of Electrical and Computer Engineering
(217) 244-3616
3104 Nick Holonyak Jr. Micro and Nanotechnology Laboratory

For More Information

Education

  • Ph.D., Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA
  • M.S., Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA
  • Bachelor of Technology, Electrical Engineering, Indian Institute of Technology, Kanpur, India

Biography

I am an expert in physics-based modeling of nanoelectronic and magnetic devices for energy-efficient computing and communication. The models I create are predictive in nature, provide guidance to experiments, reduce costs of test-structures, improve the turnaround and success rate of laboratory tests by preventing trial and error, and enable correct interpretation of experimental data. I have been actively disseminating the simulation programs I develop via the open-source platform, nanoHUB, since 2013. The purpose of my computational outreach is to strengthen the innovation loop between materials scientists, device engineers, and circuit designers and eventually enable new functionalities in the next-generation sensing, memory, computing, and communication technologies.

Academic Positions

  • [2023-present] Associate Professor, Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL
  • [2019-2023] Assistant Professor, Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL
  • [2015-2019] Assistant Professor, Electrical and Computer Engineering, New York University, Brooklyn, NY
  • [2012-2014] Postdoctoral Associate, Microsystems Technology Laboratory, Massachusetts Institute of Technology, Cambridge, MA

Other Professional Employment

  • [2006-2007] Design Engineer, Freescale Semiconductors, India
  • [2005-2006] Design Engineer, Sandisk, India
  • [2005] Component Design Engineer, Intel, India

Resident Instruction

  • EL-GY 6473 Introduction to VLSI [New York University, Fa. 2015-Fa. 2018 ]
  • EL-GY 6523 Nanoelectronic Devices [New York University, Sp. 2016-2019]
  • EE-UY 4423 Nanoelectronic Devices and Circuits [New York University, Sp. 2017-2019]
  • ECE 441 Physics and Modeling of Semiconductor Devices [Sp. 2020; Fa. 2020; Sp. 2022; Sp. 2023; Sp. 2024]
  • ECE 340 Semiconductor Devices [Fa. 2021; Fa. 2022]
  • ECE 298 The Semiconductor Chips Revolution [Fa. 2023; Fa. 2024]
  • ECE 535. Theory of Semiconductors and Semiconductor Devices [University of Illinois, Urbana-Champaign, Sp. 2025 & Fa. 2025]
  • ECE 498. Modeling and Simulation of RF Devices [Sp. 2026]

Short Courses

  • Emerging CMOS technology at 5 nm and beyond: Device options and trade-offs. IEEE International Electron Devices Meeting (IEDM), Washington D.C., Dec. 07-09, 2015.

Other Undergraduate Advising Activities

  • Organized annual hands-on summer workshop called creative circuit design C2D at NYU. The workshop was conducted every summer from 2016 to 2018, until I relocated to UIUC. This was the first of its kind workshop organized within the ECE department at NYU, aimed at inspiring high school rising juniors and seniors to build circuits and understand how electrical and computer engineering has shaped our daily lives and to further motivate them for pursuing an engineering degree in college. Each year approximately 20 high school students were selected out of a total of 100-120 applicants to participate in the one-week workshop help on the engineering campus of NYU in Brooklyn. The workshop was geared toward building circuits including light sensors, logic gates, potato batteries, AM radio circuit, and programming Raspberry pi. The basic concept underlying this workshop is to increase awareness about electrical engineering and to lead young students on a path of self- discovery. I have also steered my undergraduate and Ph.D. students to supervise portions of the workshop, providing relatable models to high school students for how an engineering career can take off. To sustain and grow the workshop in future, my plan is to submit an NSF grant proposal that supports K-12 outreach activities particularly to provide access to circuit building blocks to underrepresented minorities in high school to increase their awareness and motivate them to pursue college in STEM fields.

Research Statement

My research in theoretical device physics lies at the intersection of materials science and circuit design. I am engaged in understanding, predicting, and modeling physical phenomena in materials that drive their functional behavior and enable multifaceted applications in the domains of low-power logic and memory, brain-inspired and secure computing, and wireless communication. The device models I create are predictive in nature, provide guidance to experiments, reduce costs of test-structures, improve the turnaround and success rate of laboratory tests by preventing trial and error, and enable correct interpretation of experimental data. Because my models are multi-scale in nature, spanning from first-principles calculations to circuit-compatible implementations, my research has advanced our capability for materials-to-circuits co-design for a wide range of technologically relevant applications. This means that my computational platforms empower device technologists and circuit designers to rapidly exchange scientific ideas and strengthen the innovation loop across the design hierarchy.

Over my academic career, I have conducted foundational research in materials and devices that not only push the envelope of basic science but also have the potential to create pervasive and impactful electronic applications. For example, my work in wide bandgap semiconductors can lead to superior near-terahertz communication and sensing systems designed to access data from extreme environments. Such systems can enable major breakthroughs for several scientific investigations including energy generation, national security, and space applications. Meanwhile, I have expanded my research into power electronics applications of ultrawide bandgap semiconductors, prominently diamond and gallium oxide, which have the potential to reduce electricity losses in high-voltage transmission by more than 40% and dramatically improve the efficiency of AI data centers. My work in modeling and designing non-volatile and highly energy-efficient spintronic and ferroelectric devices can address one of the grand societal challenges related to reducing the power consumption of computing systems.

In the area of digital and high-frequency electronics, I have developed models to describe the behavior of III-nitride high-electron mobility transistors (HEMTs), photoconductive switches using wide bandgap semiconductors, Schottky-barrier transistors, graphene plasmonic interconnects, and nano-antennas that can operate in the terahertz regime. My research is the first to report a III-nitride HEMT compact model that faithfully captures the physics of quasi-ballistic electron transport—i.e., when electron scatterings are suppressed in the channel. I have also highlighted the limits, challenges, and opportunities of scaling III-nitride HEMTs down to the cryogenic temperatures, approximately 4 K, needed for interfacing of electronic circuitry with the quantum computer circuitry. My group was the first to develop a physical model interface for commercial TCAD solvers that allows accurate simulation of sub-gap excitation in diamond dual-gated (i.e., both electrically and optically) field-effect transistor, which offers complete electromagnetic interference immunity, intrinsic galvanic isolation, and compact design by eliminating bulky isolation.

I have also contributed significantly to the fundamental understanding of noisy dynamics in magnetic structures and applications of magnetic materials to nonvolatile memory, probabilistic computing, and reconfigurable circuits that are inherently secure against hardware attacks. More recently, I was invited to present at IEEE NANO, where I shared my work on multidomain switching dynamics in hafnium oxide—a material rapidly emerging as a leading candidate for non-volatile memory devices that can be seamlessly integrated with silicon CMOS to enable enhanced functionality. To tackle the multi-scale and multi-physics problems for various nanoscale devices, I have developed new numerical techniques employing GPUs that allow the massive parallelization of Monte-Carlo and various other optimization algorithms for specific applications.

I currently serve as Director of the Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP), an NSF Industry-University Cooperative Research Center that drives pathfinding semiconductor research through sustained engagement with industry. ASAP Center partners with major semiconductor companies, startups, and national labs to develop strategies for reducing the energy consumption of computing systems. The ASAP Center has opened doors to new inter-disciplinary collaborations amongst more than 15 faculty and 30 students who are working together to develop new information processing solutions with orders of magnitude improvement in system performance. Industry members include AFRL, AMD, IBM, Intel, Laboratory of Physical Sciences, MIT Lincoln Lab, Raytheon/Collins, Sandia National Lab, Seagate, Synopsys, TSMC.

Since early 2025, I have also led a statewide, CHIPS+ Act-funded initiative—the Illinois Semiconductor Workforce Network (ISWN)—to prepare the next generation of semiconductor professionals. ISWN delivers hands-on fabrication training to students at community colleges in Illinois, equipping them with the skills needed to thrive in this critical industry. By bringing together perspectives from the broader Illinois ecosystem, ISWN is developing curricula aligned with industry needs, offering career counseling, and connecting students with employers. This effort not only opens doors to high-quality jobs but also helps meet the rapidly growing workforce demands of the industry.

Graduate Research Opportunities

If you are interested in conducting your doctoral research in my group, please email me with a copy of your CV, research statement, and a short slide deck with an overview of your prior research experience and future goals. Please note that I will not be responding to inquiries that are outside of my current research interests.

Undergraduate Research Opportunities

I invite motivated undergraduate students from Electrical Engineering and Physics to reach out to me for research opportunities in the area of modeling and simulation of nanoelectronic devices, as well as the co-design and co-optimization of materials, devices, and circuits for energy-efficient computing.

Research Interests

  • Compact Modeling of wide bandgap and ultrawide bandgap semiconductor devices for high-frequency and high-power applications
  • Modeling and simulation of spin-based devices for low-power non-volatile memory and brain-inspired computing
  • Modeling of reconfigurable devices using van der Waals materials and ferroelectrics for in-memory computing

Research Areas

  • Circuits

Books Authored or Co-Authored (Original Editions)

Chapters in Books

  • S. Rakheja, A. Ceyhan, A. Naeemi. Interconnect considerations. CMOS and Beyond: Logic Switches for Terascale Integrated Circuits. K. Kuhn (Eds.), ch. 15, pp. 911-960, Cambridge University Press, 2015. (invited)
  • S. Rakheja, A. Naeemi. Communicating novel computational state variables in post- CMOS logic. IEEE Nanotechnology Magazine, vol. 7, no. 1, pp. , 2013. (invited)
  • S. Rakheja, A. Naeemi. On physical limits and challenges of graphene nanoribbons as interconnects for all-spin logic. Nanoelectronic Device Applications Handbook. J. Morris and K. Iniewski (Eds.), ch. 64, pp. 807-826, CRC Press, 2015. (invited)
  • S. Rakheja, A. Naeemi. Interconnects for alternative state variables. Graphene Nanoelectronics: From Materials to Circuits. R. Murali (Ed.), ch. 5, pp. 113-136, Springer, 2011. (invited)
  • Contributed to the chapter on Emerging Interconnects. International Technology Roadmap for Semiconductors (ITRS), 2011. (invited)

Monographs

Selected Articles in Journals

Articles in Conference Proceedings

  • Sheikh Mohd Ta-Seen Afrid, He Lin Zhao, Arend M. van der Zande, and Shaloo Rakheja. 2026. Strain-Driven Control of Carrier Injection at Pristine and Defective n- and p-Type Metal–TMD Interfaces. In VLSI International Symposium on Technology, Systems, and Applications. (April 13-17).  
  • Samdani, G.M., Shukla A. and Rakheja S., 2025, June. A custom end-to-end modeling suite for ferroelectric devices. In Device Research Conference (June 22-25), DRC. 
  • Voss, L., Shao, Q., Frye, C.D., Evans, D., Chatterjee, B., White, E., Soumak, N., Rakheja, S., Malakoutian, M., Chowdhury, S. and Giardine, F., 2025, October. Diamond Optically Gated Junction Field Effect Transistors. In 248th ECS Meeting (October 12-16, 2025). ECS.
  • Samdani, G.M., Shukla, A. and Rakheja, S., 2025, July. Switching Dynamics of Multidomain Ferroelectric Devices: Physical Modeling Approaches, Experimental Validation, and Design-Space Exploration. In 2025 IEEE 25th International Conference on Nanotechnology (NANO) (pp. 217-221). IEEE.
  • Tunga, S., Grupen, M. and Rakheja, S., 2025. A full 3D TCAD framework for nanosheet transistors including quantum-confined channels.
  • Rakheja, S., 2024, October. A materials-and devices-centric approach to neuromorphic computing. In Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (pp. 1-9).
  • Tunga A., Kang J., Zhao Z., Shukla A., Zhu W., Rakheja S. 2024. Modeling of content addressable memory using reconfigurable transistors. In Device Research Conference, June 23-26, College Park, MD, USA.
  • Tunga A., Shur M., Grupen M., Hill D., Rakheja, S. 2024. Simulating Terahertz Plasma Oscillations in Transistors. In International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep. 25-27, San Jose, CA.
  • Zhou, Y., Ma, H., Yu, J., Shameem, T., Salehi, Z., Rakheja, S., Li, E. and Schutt-Aine, J.E., 2024, May. Latency Insertion Method for Accelerated Simulation of Memristor Crossbar Array in Neuromorphic Chip. In 2024 IEEE 74th Electronic Components and Technology Conference (ECTC) (pp. 2200-2204). IEEE.
  • Qian S., Shukla A., Rakheja S. Effect of thermal noise on the field-assisted spin-orbit-torque-driven dynamics in Mn3Sn. Bulletin of the American Physical Society, Minneapolis, Minnesota, March 3-8, 2024.
  • Pulugurtha S., Daniel K., Rakheja S. Spin Relaxation in Strained Graphene-TMD Heterostructures using Ab Initio Methods. Bulletin of the American Physical Society, Minneapolis, Minnesota, March 3-8, 2024. (Best in session)
  • Shukla S., Qian S., Rakheja S. Field-assisted spin-orbit-torque-driven dynamics in monodomain Mn3Sn with perpendicular magnetic anisotropy. IEEE and APS 68th Annual Conference on Magnetism and Magnetic Materials, Dallas, TX, Oct. 30-Nov. 03, 2023.
  • White E., Tunga A., Miller N.C., Grupen M., Albrecht J., Rakheja S. Large-signal modeling of GaN HEMTs using Fermi kinetics and commercial hydrodynamics transport. In Device Research Conference (DRC), Santa-Barbara, CA, June 25-28, 2023
  • Shukla A., Zhu W., and Rakheja S. All-ferroelectric implementation of Ising machines. In Semiconductor Research Corporation (SRC), Techcon, Austin, Texas, September 10-12, 2023
  • Tunga, A., Zhu W.; and Rakheja S. Effects of Process Variability on Performance of Reconfigurable Transistors based Content Addressable Memory. In Semiconductor Research Corporation (SRC), Techcon, Austin, Texas, September 10-12, 2023.
  • Shukla, A., Heller, L., Morshed, M. G., Rehm, L., Ghosh, A. W., Kent, A. D., and Rakheja, S. (2023, April). A True Random Number Generator for Probabilistic Computing using Stochastic Magnetic Actuated Random Transducer Devices. In 2023 24th International Symposium on Quality Electronic Design (ISQED) (pp. 1-10). IEEE
  • M.G. Morshed, A. Shukla, L. Rehm, L. Heller, Y. Xie, S. Ganguly, S. Rakheja, A.D. Kent, and A. Ghosh. Probabilistic spin-torque switching of perpendicular magnetic tunnel junctions under short current pulses. Bulletin of the American Physical Society, Las Vegas, NV, March 5-10, 2023.
  • J. Kang, S. Rakheja, and W. Zhu. Reconfigurable logic transistors based on 2D heterostructures. Bulletin of the American Physical Society, Las Vegas, NV, March 5-10, 2023.
  • Y. Dong and S. Rakheja. Role of deep levels in semi-insulating gallium arsenide pulse-compression photoconductive switches. Bulletin of the American Physical Society, Las Vegas, NV, March 5-10, 2023.
  • J. Kang, S. Rakheja, and W. Zhu. Reconfigurable Transistors based on Van der Waals Heterostructures. In Semiconductor Research Corporation (SRC) Techcon, Austin, Texas, September 18-20, 2022.
  • Z. Zhao, K. Xu, J. Liu, W. Jiang, H. Ryu, S. Rakheja, T. Low, and W. Zhu. Nanoscale devices based on two-dimensional and ferroelectric materials. In Device Research Conference (DRC), Columbus, Ohio, June 26-29, 2022.
  • E. Cruz-Camachu, S. Qian, A. Shukla, N. McGlohon, S. Rakheja, and C. Carothers. Evaluating performance of spintronics-based spiking neural network chips using parallel discrete event simulation. In SIGSIM Conference on Principles of Advanced Discrete Simulation, Atlanta, GA, June 08-10, 2022.
  • B. Wu, S. Rakheja. Modeling of the charge-voltage characteristics of AlScN/AlN/GaN heterostructures. In Device Research Conference (DRC), Columbus, Ohio, June 26-29, 2022.
  • K. Li, T. Matsuda, E. Yagyu, K.H. Teo, S. Rakheja. Trapping phenomena in GaN HEMTs with Fe- and C-doped buffer. In Device Research Conference (DRC), Columbus, Ohio, June 26-29, 2022.
  • K. Li., S. Rakheja. Physical Modeling of Quasi-ballistic GaN HEMTs Operating at Cryogenic Temperatures. In Compound Semiconductor Week (CSW), Michigan, Ann Arbor, June 1-3, 2022.
  • A. Shukla, S. Qian, S. Rakheja. Dipolarly coupled nanomagnets as hardware emulators of neurons for brain-like computing systems. In Bulletin of the American Physical Society, Chicago, Mar. 14-18, 2022.
  • S. Shah, A. Mahmood, W. Echtenkamp, J. Wang, M. Street, T. Komesu, P. Dowben, P. Buragohain, H. Lu, A. Gruverman, A. Parthasarathy, S. Rakheja, C. Binek. Voltage-controlled Neel vector rotation in zero magnetic field in high-TN magnetoelectric thin films. In Bulletin of the American Physical Society, Chicago, Mar. 14-18, 2022.
  • A. Tunga, X. Li, S. Rakheja. Modeling-based design and benchmarking of Al-rich AlGaN 3D nanosheet MOSFET and MOSHEMTs for RF Applications. In 79th Device Research Conference (DRC), Virtual, June 20-23, 2021.
  • A. Shukla, S. Rakheja. Terahertz auto oscillations in non-collinear coplanar metallic antiferromagnets. In 79th Device Research Conference (DRC), Virtual, June 20-23, 2021.
  • A. Shukla, S. Rakheja. Spin torque driven self- oscillations in non-collinear coplanar antiferromagnets. In American Physical Society (APS) March Meting, Mar. 15-19, 2021 (Virtual).
  • A. Parthasarathy, S. Rakheja. Spin-Torque-Induced Chaos in Antiferromagnets. In Magnetism and Magnetic Materials Conference, Virtual, Nov. 02-06, 2020.
  • K. Li, E. Yagyu, H. Saito, K. H. Teo, S. Rakheja. Compact modeling of gate leakage phenomenon in GaN HEMTs. In International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Virtual, Sep. 23-Oct. 06, 2020.
  • A. Parthasarathy, S. Rakheja. Ultrafast and Energy-efficient Antiferromagnetic Memory and Oscillator. In SRC Techcon, Austin, Texas, Sep. 14-17, 2020.
  • A. Shukla, A. Parthasarathy, S. Rakheja. Analytic modeling of switching time dynamics of monodomain ferromagnets with biaxial energy landscape. Bulletin of the American Physical Society, 65, Mar. 5, 2020.
  • A. Parthasarathy, N. Rangarajan, S. Rakheja. Strain-driven spin-Hall antiferromagnetic memory for 180° switching. Bulletin of the American Physical Society, 65, Mar. 5, 2020
  • S.M. Farzaneh, S. Rakheja. Effective Hamiltonian for Extrinsic Spin-Orbit Coupling in 2D Materials. Bulletin of the American Physical Society, 65, Mar. 5, 2020.
  • S. Rakheja, L. Huang, S. Hau-Riege, S.E. Harrison, L.F. Voss, A.M. Conway. Modeling and Design of SiC-based High-Frequency Photoconductive Switches. In IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2020, pp. 1-4, doi: 10.1109/EDTM47692.2020.9117837.
  • A. Parthasarathy, S. Rakheja. Theory of spin-current-induced auto-oscillations in a biaxial antiferromagnet. In Magnetism and Magnetic Materials Conference, Las Vegas, NV, Nov. 04-08, 2019.
  • P. Sengupta, S. Rakheja. Spin-valley Coupled Caloritronics with Strained Honeycomb Lattices. In 2019 Device Research Conference (DRC), Ann Arbor, MI, USA, 2019, pp. 81-82, doi: 10.1109/DRC46940.2019.9046413.
  • S. Rakheja, M. Flatte, A. D. Kent. Voltage-controlled topological spin-switch for approximate computing. Joint MMM-Intermag Conference, Washington D.C., Jan. 14-18, 2019.
  • K. Li, S. Rakheja. A unified charge-current compact model of gallium nitride transistors for RF and digital applications. IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Singapore, Mar. 12-15, 2019. (Invited)
  • A. Parthasarathy, S. Rakheja. Phenomenology of magnetoelectric switching of antiferromagnetic domain. Joint MMM-Intermag Conference, Washington D.C., Jan. 14-18, 2019.
  • K. Li, S. Rakheja. Design and modeling of III-Nitride HEMTs for extremely linear RF operation. Materials Research Society (MRS) Meeting, Boston, Massachusetts, Nov. 25-30, 2018.
  • S. Farzaneh, S. Rakheja. Spin relaxation in 2D semiconductors with an elliptic band structure. Materials Research Society (MRS) Meeting, Boston, Massachusetts, Nov. 25-30, 2018.
  • S. Patnaik, N. Rangarajan, J. Knechtel, O. Sinanoglu, S. Rakheja. Advancing hardware security using polymorphic and stochastic spin-Hall effect devices. Design Automation and Test in Europe (DATE), Dresden, Germany, Mar. 19-23, 2018.
  • K. Li, S. Rakheja. Nonlinearity of III-nitride HEMTs for RF applications--Analytical modeling and device design for enhanced dynamic range. Materials Research Society (MRS) Meeting, Boston, Massachusetts, Nov. 26-Dec. 01, 2017.
  • S. Rakheja, N. Kani. Spin-torque nano-oscillator driven by spin pumping for phase- based neuromorphic computing. Materials Research Society (MRS) Meeting, Boston, Massachusetts, Nov. 26-Dec. 01, 2017.
  • S. Rakheja, K. Li. Graphene-based plasma wave interconnects for on-chip communication in the terahertz band. Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop, Berkeley, California, Oct. 19-20, 2017.
  • N. Kani, S. Rakheja. Analytical reliability models for two-magnet systems. MAGNET, The 5th Italian Conference on Magnetism, Assisi, Italy, Sep. 13-15, 2017.
  • S. Rakheja, N. Kani. Polymorphic spintronic logic gates for hardware security primitives-Device design and performance benchmarking. Nano Architectures (NANOARCH), Newport, Rhode Island, July 25-26, 2017.
  • S. Rakheja, P. Sengupta. Graphene nanoribbon plasmonic waveguides: Fundamental lim- its and device implications. Device Research Conference (DRC), Santa Barbara, California, June 22-25, 2014.
  • A. Naeemi, A. Ceyhan, V. Kumar, C. Pan, R. Mousavi, S. Rakheja. BEOL scaling limits and next generation technology prospects. Design Automation Conference (DAC), San Francisco, California, June 02-06, 2014 (Invited).
  • S. Rakheja, H. Wang, T. Palacios, I. Meric, K. Shepard, D. Antoniadis. A unified charge- current compact model for ambipolar operation in quasi-ballistic graphene transistors: Experimental verification and circuit-analysis demonstration. IEEE Electron Devices Meeting (IEDM), Washington D.C., Dec. 09-12, 2013
  • S. Rakheja, V. Kumar, A. Naeemi. Graphene nanoribbons for all-spin logic: Effects of dimensional scaling on spin transport. Semiconductor Research Corporation (SRC), TECHCON, Austin, Texas, Sep. 10-12, 2012 (Won the best in session award).
  • S. Rakheja, A. Naeemi. Compact modeling of spin-transport parameters in semiconducting channels in non-local spin-torque devices. IEEE NANO, Birmingham, U.K., Aug. 20 – 23, 2012.
  • S. Rakheja, V. Kumar, Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations. IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, California. March 18 – 22, 2012.
  • S. Rakheja, A. Naeemi. Interconnect analysis in spin-torque devices: Performance modeling, optimal repeater insertion, and circuit-size limits. IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, California. March 18 – 22, 2012.

Pending Articles

Other Publications

Patents

  • Pulse Compression Photoconductive Semiconductor Switches filed jointly with Lawrence Livermore National Laboratory on October 15, 2021 (U.S. Patent Application No. 17/502,681)
  • High electron mobility transistor (HEMT) comprising stacked nanowire or nanosheet heterostructures filed on April 06, 2021 (U.S. Patent Application No. 63/171,443)

Journal Editorships

  • Guest Editor for IEEE Transactions on Components, Packaging and Manufacturing Technology Special Section on Heterogeneous Integration for Neuromorphic Computing, 2024
  • Editor for ACM Journal on Emerging Technologies in Computing Systems. Term Started in 2022.
  • Guest Editor for Applied Physics Letters Special Topic "Dimensional Scaling of Material Functional Properties to meet Back-End-of-Line (BEOL) Challenges" (2022). url: https://bit.ly/3FNoxB2

Conferences Organized or Chaired

  • Technical Program Committee Member, IEEE Device Research Conference, 2025
  • Technical Program Committee Member, IEEE Device Research Conference, 2023
  • Technical Program Committee Member, IEEE Device Research Conference, 2022
  • Technical Program Committee Member, IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021
  • Technical Program Committee Member, IEEE Device Research Conference, 2021
  • Technical Program Committee Member, IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020
  • Technical Program Committee Member, Design Automation and Test in Europe (DATE) Conference, 2020
  • Technical Program Committee Member, IEEE VLSI Design, 2019
  • Technical Program Committee Member, IEEE/ACM Design Automation Conference (DAC), 2017-2018
  • Technical Program Committee Member, IEEE VLSI Design, 2018
  • Technical Program Committee Member, IEEE International Electron Devices Meeting (IEDM), 2018
  • Technical Program Committee Member, IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2017

Research Honors

  • State Medal (2000)
  • Sangeeta Goel Memorial Award (2001)
  • Academic Excellence Award (2002-2003)
  • Intel PhD Fellowship (2011-2012)
  • Graduate Research Excellence Award (2012)
  • Best in Session Award Semiconductor Research Corporation (SRC), TECHCON, 2012 (2012)
  • NYU Goddard Junior Faculty Fellowship (2018-2019)
  • Intel Alumni Endowed Faculty Fellow (2023)
  • Public Voices Fellow (2023-2024)
  • Engineering Council Outstanding Advisor Award (2024) (2024)
  • Selected by the US National Science Foundation and the Ireland Science Foundation to participate in a workshop to "Foster Trans-Atlantic Inter-disciplinary Collaborations" in Semiconductors & Microelectronics (2024)

Public Service Honors

  • IEEE Electron Devices Society (EDS) golden reviewer (2014-2017)

Recent Courses Taught

  • ECE 298 RR - Semiconductor Chips Revolution
  • ECE 340 - Semiconductor Electronics
  • ECE 441 - Physcs & Modeling Semicond Dev
  • ECE 498 SR - Model & Simulation RF Devices
  • ECE 535 (PHYS 565) - Theory of Semicond & Devices