After three years, CAEML celebrates its accomplishments


Allie Arp, Coordinated Science Lab

Now in its third year, the Center for Advance Electronics through Machine Learning (CAEML) is funding 11 research projects, including seven new projects.

“The new research projects leverage the early work done through the center," said CAEML Director Elyse Rosenbaum, the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering. "For example, in the initial set of projects, we developed optimization techniques that are especially well suited for electronic system design and identified behavioral model classes
Elyse Rosenbaum
Elyse Rosenbaum
that can be used to represent a wide variety of integrated circuits. In the center’s current research portfolio, there is an increasing focus on security applications and on design planning, e.g., PPA (power-performance-area prediction) and DTCO (design-technology co-optimization.”

The principal investigators (PI) of the projects are spread out among CAEML’s three partner institutions, the University of Illinois at Urbana-Champaign, North Carolina State University (NCSU), and the Georgia Institute of Technology. The membership fees paid by the center’s 12 industry partners provide the research funds. Each industry member has a representative on the board that votes on which projects to support. The industry partners joined CAEML for the opportunity to develop relationships with graduate students, options for licensing or intellectual property acquisition, and to see what might be next for the industry.

The new projects for 2019 are as follows:

  • Netlist-to-PPA Prediction Using Machine Learning, PI Sung Kyu Lim of Georgia Tech, two-year project
  • Fast, Accurate PPA Model-Extraction, PI Rhett Davis of NCSU, two-year project
  • RNN Models for  Computationally-Efficient Simulation of Circuit Aging Including Stochastic Effects, PI Elyse Rosenbaum of Illinois, two-year project
  • High-dimensional Structural Inference for Non-linear Deep Markov or State Space Time Series Models, PI Dror Baron of NCSU, one-year project
  • High-Speed Bus Physical Design Analysis through Machine Learning, PI Xu Chen, Illinois, and Madhavan Swaminathan, Georgia Tech, two-year project
  • Design Space Exploration using DNN, PI Madhavan Swaminathan of Georgia Tech, two-year project
  • Enabling Side-Channel Attacks on Post-Quantum Protocols through Machine-Learning Classifiers, PI Aydin Aysu of NCSU, two-year project

The selected projects are consistent with CAEML’s stated mission “to enable fast, accurate design and verification of microelectronic circuits and systems by creating machine learning algorithms to derive models used for electronic design automation.“

By speeding up the design and verification of microelectronic circuits and systems, CAEML will reduce development cost and time-to-market for manufacturers of microelectronic products. The center further seeks to eliminate the computational hurdles that often make simulation-based design optimization infeasible, thereby allowing engineers to produce better designs without compromising time-to-market, where a better design may be lower power, more reliable, more secure, and/or lower cost.

For more information about CAEML, visit its website.