1/5/2022 Jenny Applequist, Coordinated Science Lab
CSL’s Pavan Hanumolu is contributing to the The Intel® Research Center for Integrated Photonics for Data Center Interconnects by creating more energy-efficient interconnects.
Written by Jenny Applequist, Coordinated Science Lab
Data centers have become an integral feature of the modern world. Whether they’re enabling global commerce or just helping you share your cat videos with your friends, they play a foundational role in the storage, transmission, and processing of the immense quantities of data that continuously flow around the globe. But the services they provide come at a price: massive consumption of energy. A single data center can gobble up more power than an entire mid-sized town, and together the world’s data centers are responsible for over 1% of humanity’s electricity use.
As part of a new Intel research center, CSL’s Pavan Hanumolu is leading one effort to chip away at that problem.
The Intel® Research Center for Integrated Photonics for Data Center Interconnects has been established to innovate significant power and performance improvements to data center communication, and various university teams are working on different pieces of this challenge. “I sit somewhere in the middle of the integration stack,” says Hanumolu, who is a professor and Intel Alumni Scholar in Electrical & Computer Engineering. “My part is to sense received signals with as much fidelity as possible.” If he can find ways to detect fainter optical signals without error, that would enable energy savings by making it possible to use a lower-intensity light signal to transmit data.
Specifically, his project will pursue solutions in three areas.
The first goal is an ultra-low-power, highly sensitive optical receiver that uses an approach, recently developed by his group, called “duobinary sampling”—rather than the noisy, power-hungry state-of-the art method—to recover transmitted data. Receivers, whose job is to detect an incoming optical signal, turn out to be a major bottleneck: they have good noise performance if they’re low-bandwidth, but if you try to make them wide-bandwidth, you get poor noise performance. “But in reality, what do we want?” asks Hanumolu. “As always, we want very wide bandwidth and low noise! So how do we overcome this fundamental trade-off?” His team will try to reduce the bandwidth to reduce the noise, and also try to reduce the resulting distortion through use of the duobinary sampling (which avoids the use of feedback loops that makes existing approaches so costly).
The second goal is to create clock and data-recovery architectures that can achieve very high jitter tolerance in a power-efficient manner. Data centers are getting bigger and bigger, and wires are getting longer and longer: “As the size of the data center increases... the same techniques must work at longer wire lengths,” Hanumolu explains. But when you increase distances, you get more noise, which appears as jitter. So if he can improve jitter tolerance, that would increase the possible wire lengths, meaning that the same data transmission rate could be maintained over longer distances.
The third goal is to develop clock-multiplier and multi-phase-generating phase interpolators based on fractionally injected oscillators. Hanumolu characterizes this piece of the project as “very nitty-gritty” and explains that conventional phase interpolators have limitations in performance linearity and power efficiency that could be overcome with this effort.
The energy savings achieved by the developed solutions will be demonstrated by means of experiments conducted in Intel labs as well as UIUC facilities. The goal is to demonstrate better than 0.25 pico-Joule per bit energy efficiency for the overall system.
The award from Intel will run for three years.