Rosenbaum awarded grant to simulate and predict integrated circuit failure due to electrostatic discharge

5/17/2024 Amber Rose

Written by Amber Rose

A woman stands at a laboratory counter with science equipment around her. She looks at the camera and smiles
Elyse Rosenbaum

Electrical & computer engineering professor Elyse Rosenbaum has been awarded a $220,000 grant from the Semiconductor Research Corporation (SRC) for her project titled “CDM Reliability Prediction: From the Test Circuit to the IC Product.” The project aims to simulate charge device model (CDM) electrostatic discharge (ESD) events inside integrated circuits with high precision and correctly predict what the failure level of the device will be.

CDM is a model that emulates the type of ESD that is the largest single cause of failures during the production of integrated circuits, more commonly known as chips.

All of the objects around us, including our skin, have some static charge, and if you have ever walked across carpet in socks during the winter and then touched a light switch, you are familiar with ESD. The difference between a human and a chip, though, is that humans aren’t damaged by the shock felt from an ESD event. The transistors and wires in an integrated circuit, however, are very tiny and therefore vulnerable. As Rosenbaum puts it, if the current generated from an ESD event were not diverted away from the core of an integrated circuit, hundreds of billions of amps per square centimeter would flow through the on-chip elements. It’s a high current density, and the elements are almost certainly going to melt.

“We need to shunt the current away from the tiny little transistors and wires and provide a safe path for the current to flow between any random pair of pins on our integrated circuit package. And we do that by putting ESD clamps and protection devices at all the input pins, the output pins, the power supply pins and the ground pins,” explains Rosenbaum, who is also the Melvin and Anne Louise Hassebrock Professor in ECE.

Normally, the ESD clamps are off, so they don’t interfere with the normal operation of the circuit. If an ESD event is detected, those devices turn on and act like a short circuit so that all the current will flow through the protection circuitry.

However, “as technology is scaled and the feature sizes get smaller and smaller, all of the interconnects and transistors become progressively more vulnerable to ESD-induced damage,” Rosenbaum says. “We have this problem that as the technology is getting more vulnerable, we want to increase the size of the protection devices, but that would increase the loading on the active circuitry and reduce performance. So, we need to very carefully manage the conflicting requirements for high performance, small area and high reliability. This can be done with very clever circuit design and understanding the physics of failure.”

Manufacturing of modern integrated circuits is expensive, making it advantageous to first simulate circuit designs to determine whether they will pass ESD qualification testing. For this project, Rosenbaum plans to demonstrate that CDM ESD events inside integrated circuits can be simulated with high precision and correctly predict what the failure level will be. To develop that simulation capability, it will be necessary to validate the simulations with hardware measurements. Rosenbaum’s team has proposed a specialized experimental set up that will allow them to make those measurements.

“What I like about this project is that it’s not just experimental and it’s not just modeling/simulation, it’s both,” Rosenbaum says. “We’re doing chip design, having the chips manufactured and testing them. But we’re also building models of the chips and simulating them. So, we hit all the different aspects, both the physical experimentation and the mathematical modeling, and I’m excited about the breadth of this work.”

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This story was published May 17, 2024.