CSL/ITI Professors present at prestigious ERI Summit

Started in 2017, the Electronics Resurgence Initiative (ERI) is a five-year $1.5 billion investment in defense electronic systems by the Defense Advanced Research Project Agency (DARPA). Each year, researchers leading aspects of the 19 different programs funded by the initiative are invited to share their research at an annual summit. This summer, CSL Professor Naresh Shanbhag and fellow Information Trust Institute (ITI) Professor Sarita Adve were among the invited presenters.

MRAM-based Deep In-memory Architectures

Under the FRANC (Foundations for Novel Compute) program, this project is a collaboration between an Illinois team led by CSL's Shanbhag, including CSL Professor Pavan Hanumolu, Princeton University, GLOBALFOUNDRIES (GF) and Raytheon Missile Systems, aims to develop novel computing technologies to addresses the needs of autonomous sensory platforms that make mission-critical decisions in real-time. Since the project was introduced by CSL last summer, the group demonstrated multiple approaches to design deep in-memory architectures (DIMAs) using GF’s MRAM device within the context of a Shannon-inspired model of computation.

The developments required the group to discover new design techniques that leverage the MRAM device’s unique features of high-density and non-volatility in the context of DIMA. These MRAM-based DIMA approaches were found to provide between 2-to-3 orders-of-magnitude reduction in the energy-delay product of decision-making as compared to the conventional von Neumann architecture.

“Based on the outcomes of the past year, our project was selected for continued funding in the next phase of the FRANC program which started in April 2019,” said Shanbhag, Jack S. Kilby Professor of Electrical and Computer Engineering. “We are looking forward to testing the first generation DIMA chips that are currently being fabricated, and making plans for the design of the second generation chips. It is exciting to be able to see the technologies we develop being useful in industrial settings.”

As part of this new phase of funding, the research team designed the world’s first MRAM-based DIMA chips. These chips were taped-out – the final step in the pre-fabrication process -- in collaboration with GF’s field application engineers in June and are currently being fabricated in GF’s Dresden and Singapore facilities.

The first generation chips will be used to characterize the properties of the MRAM-based DIMA technology, and the second generation chips will be able to implement real-life applications in RMS facilities. The group will also be working with GF to develop MRAM-based DIMA synthesis tools so that designing future chips will be facilitated.

While presenting their work at the summit, the group attracted the attention of Lisa Porter, Deputy Under Secretary of Defense for Research and Development (DUSD(R&E)) and many others.

“Our work attracted a lot of attention from various companies and DoD organizations wanting to collaborate with us,” said Shanbhag, professor of electrical and computer engineering. “It also became clear that our teaming arrangement of academia, a commercial semiconductor company (GF) and a defense company (RMS) was unique and one of our strengths since it provides us with an opportunity to demonstrate the value of an emerging device technology in DoD and commercial applications.”

Cognitive Heterogeneous Systems

ITI's Adve represented the EPOCHS (Efficient Programmability of Cognitive Heterogeneous Systems) project, funded by the DSSOC (Domain-Specific Systems-on-Chip) program within the ERI. The project is a collaboration with two other Illinois faculty, Vikram Adve, CSL Professor and Donald B. Gillies Professor in Computer Science (CS), and Sasa Misailovic, CS Assistant Professor, as well as researchers at IBM, Columbia University, and Harvard University. The group tackled the challenge of achieving continuous performance gains from general computer hardware, a task that has become increasingly challenging because of the last decade of advances in technology.

Designers are currently focused on designing more specialized computer architectures that consist of many accelerators, each speeding up a different portion of the computation. The EPOCHS project is developing the hardware and software technologies to build and program such systems efficiently, using cognitive connected vehicles as an example of a target application domain. The Illinois team is responsible for the compiler, which is central to the programmability and energy efficiency of the chip, and for the memory system architecture which is central to the integration of the different accelerators and the efficiency with which they communicate. Adve presented the team’s research on both of these fronts and her presentation was well received, especially the proposed addition of the Spandex coherence interface, which enables efficient integration of widely disparate computational units and accelerators that use a variety of coherence mechanisms.

“After all the positive feedback we received at the summit, I am even more excited about implementing Spandex as part of the prototype chip that our EPOCHS team is working to tape out – it will be exciting to see the ideas in action on a real system,” said Sarita Adve, Richard T. Cheng Professor in CS. “We are also excited that the talk opened up discussions about directions our work needs to take to influence IBM’s products – we look forward to a broader set of collaborations with IBM.”

Underlying their research is the observation that clean interfaces are critical to the efficiency and programmability of heterogeneous systems. For the memory system, Spandex provides such an interface for efficient integration of heterogeneous coherence mechanisms. Spandex’s frictionless integration provides higher performance, lower energy, and much less complex design than the current state of the art. Over the last year, the Illinois team adapted Spandex for the application domain targeted by EPOCHS and showed even higher efficiency. For the software stack, the team has proposed Heterogeneous Parallel Virtual Machine (HPVM), a compiler intermediate representation and infrastructure that builds on the successful LLVM compiler from Vikram Adve’s group, to enable efficient heterogeneous resource management and optimization.

The team’s work attracted a lot of interest at the summit that encouraged Adve and her team.

“There was interest from corners I did not anticipate, such as government labs dealing with problems with heterogeneous system integration for high performance computing,” she said. “The talk seems to have reinforced the need for more investment from government agencies put towards solving this problem. Multiple practitioners and researchers also expressed they want to use HPVM and we plan to make it publicly available soon to enable broader adoption.”