A modern smartphone offers computing capabilities that used to require a room-sized mainframe computer. It’s a triumph of engineering that was enabled by years of tireless work to make transistors smaller and smaller—efforts that have brought tremendous benefits, such as faster computation. However, it has come at a price: since breakdown voltage—that is, the minimum voltage that causes an insulator to start conducting electricity—is linearly proportional to feature size, the shrinking of the devices has also reduced the gate breakdown voltage. At the same time, the risk of thermal failure has increased.
“By making devices, and wires, smaller, we are squeezing more current into a smaller volume,” explains CSL’s Elyse Rosenbaum. “Thermal failure occurs when current density is too high.”
By design, voltages and current densities are maintained at safe levels during normal operation; however, they exceed safe levels during an electrostatic discharge (ESD) event unless the discharge current is effectively shunted away from the vulnerable devices by an on-chip ESD protection circuit. Unfortunately, the on-chip protection can reduce circuit performance, counteracting the increases that were obtained by feature size scaling. Careful optimization is needed to balance performance and reliability.
Now, under new funding from the Semiconductor Research Corporation (SRC), Rosenbaum is developing new ways to model ESD protection devices. If she succeeds, designers will gain an inexpensive way to identify unsafe levels of stress before an integrated circuit is fabricated, allowing them to modify the design before costly prototypes have been created.
“All integrated circuits today are simulated—actually many, many times—before they’re manufactured, because it takes millions of dollars to manufacture what might be a prototype but is hopefully your first working design,” she explains. “And the only way a chip has even a prayer of passing qualification testing on the first ‘silicon spin,’ the first design, is if the models being used and the circuit simulations are highly accurate.”
For ESD devices, the necessary modeling ability hasn’t existed. Designers have dealt with the gap by “overdesigning,” making ESD protection devices bigger than necessary to guarantee that the circuit would be protected. However, ever-shrinking sizes mean that designers can no longer get away with such an approach; too-large protection devices have too much of a negative impact on performance.
Specifically, in the new project, Rosenbaum, who is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering, is working on a methodology for creating charge-based compact models of ESD protection devices and for verifying that the resulting models correctly represent the devices’ responses to arbitrary high-amplitude stimuli. The models will also accurately represent the modeled devices under normal operating conditions. Rosenbaum intends for the approach to rectify the shortcomings of existing strategies for ESD compact modeling, such as inaccurate AC representation of devices in their off state, poor numerical stability, and parameter extraction procedures that are difficult to perform, among others.
Notably, the need to model on-chip ESD protection devices during normal circuit operation is new. It’s yet another reflection of the increasingly stringent requirements imposed by reduced feature sizes. “We’re pushing things to the performance limits,” says Rosenbaum. “In the past... we didn’t worry too
much about how the protection circuit interacted with the rest of the circuit under normal operating conditions. Now we’re pushing those operating conditions to the point where the parasitic effects of a protection circuit become important. So we need models that cover a wider range of operating conditions.”
The SRC project is entitled “Demonstrably Generalizable Compact Models of ESD Devices” and will run for three years.