Innovative circuits architecture earns CSL researchers DAC/ISSCC award
CSL researcher Yun Chiu and his student Wenbo Liu have received the 46th DAC/ISSCC Student Design Contest award for their work on a time-interleaved architecture for data-conversion circuits.
The new technique will lead to more energy efficient and faster digital video signal processing systems, such as Blu Ray recorders.
"We want to minimize power consumption as much as possible to preserve the battery life of such systems," said Liu, a graduate student in electrical and computer engineering at the University of Illinois at Urbana-Champaign.
Liu's research built on previous work done by his advisor, Chiu, who had applied a similar adaptive digital error-correction algorithm to a single pipelined analog-to-digital converter (ADC).
As outlined in the paper, "A 600MS/s 30mW 0.13μm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization," Liu's research found that the treatment could also be applied to a bank of time-interleaved power-efficient successive-approximation ADCs. The key is a series of adaptive algorithms that detect path mismatches and automatically and simultaneously correct them using energy-efficient digital post-processing in deeply scaled CMOS technology.
By removing the errors inherent to time interleaving, the approach promises lower power consumption and faster speed in the critical digitization process. In addition to Blu Rays and other video applications, the technology can also be utilized in multi-gigabits-per-second wired and wireless communication systems in the future, such as the 60-GHz and UWB radios, the 10-Gbps Ethernet, etc.
The paper was presented at the International Solid-State Circuits Conference (ISSCC) in San Francisco in February. It is believed to be the first paper presented by an Illinois student at the conference in a decade. The award will be presented to the researchers at the Design Automation Conference (DAC) in San Francisco in July.