Intel grant funds CSL research to use high-level synthesis for acceleration

CSL Associate Professor Deming Chen recently received a 1-year, $25,000 gift from Intel to research methods for speeding up computing while maximizing power efficiency. Chen, an associate professor of electrical and computer engineering, expects Intel to renew the gift for a second year.

Deming Chen

The project is titled “High-Level Synthesis for Accelerator Evaluation and Generation.” Researchers will focus on increasing performance and power efficiency mainly by restructuring a programming language called CUDA so that it will run on FPGAs, or field-programming gate arrays. CUDA code was originally created for NVIDIA’s graphic processing unit (GPU) and has the advantage of high performance. FPGAs on the other hand are a type of semiconductor chip that is highly adaptable and power efficient. Both the CUDA code and FPGA are intrinsically parallel, “so it makes sense to use the two,” Chen said, an associate professor in electrical and computer engineering at the University of Illinois at Urbana-Champaign.

However, translating CUDA code to run on FPGAs can be lengthy and complicated for a programmer to do manually. That is why researchers propose to use high-level synthesis, which means they will use a program to automatically translate the CUDA code. This will create a new CUDA-to-FPGA flow called FCUDA, and will therefore create a common frontend language that is practical and user-friendly, Chen said.

The current version of the FCUDA compiler was created through collaboration with CSL Professor Wen-Mei Hwu’s group, as well as Professor Jason Cong’s group at UCLA and Illinois' Advanced Digital Sciences Center in Singapore. Intel will sponsor four new tasks leveraging and extending the FCUDA framework.

The goal of the first task is to determine which parts of a program would benefit from this acceleration, which accelerators should be used, and what the benefits would be for certain applications. The goal of the second task is to look at communication modeling and optimization, both on and off the FPGA chip. The third task will target Intel’s systems specifically, making the FCUDA flow work for real applications that are important to Intel. Finally, the fourth task will be to start implementing other features that can further improve performance, portability and usability. Researchers will do this by extending their work into other languages, reducing users annotations, and working with multiple CUDA kernels simultaneously.